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16-bit, 500 ksps pulsar ? dual, 2-channel simultaneous sampling adc ad7654 rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features dual, 16-bit, 2- channel simult a neous sampli ng adc 16-bits resol u ti on with no missing codes thro ughput: 500 ksps (nor mal mode) 444 ksps (impulse mode ) inl: 3.5 lsb max (0.0 053 % of full scale) snr: 89 db typ @ 1 00 k hz thd: ?100 db @ 10 0 kh z analog input voltage range: 0 v to 5 v n o pipeline delay parallel and se rial 5 v/3 v inte rface spi?/qspi?/microwire?/dsp-compatible single 5 v supp ly operation power dissipati o n: 120 mw typica l 2.6 mw @ 1 0 k s ps package: 48- le ad q u ad flatpa ck (lqfp) or 48-lea d fra m e chip scale package (lfcsp) low cost applic ati o ns ac motor contr o l 3-phase power control 4-channel dat a acquisition uninterrupted power supplies communications func tio n a l block di agram control logic and calibration circuitry a/b 16 d[15:0] busy cs ser/par ognd ovdd dgnd dvdd serial port byteswap rd avdd agnd refx refgnd pd rese t cnvst inan switched cap dac ad7654 ina1 impulse mux eoc ina2 a0 inb1 inbn inb2 track/hold 2 parallel interface 03057- 001 clock mux mux fi g u r e 1 . table 1. pulsa r ? sel e ction type / ksps 100 - 250 500 - 570 800 - 1000 >1000 pseudo differential ad7660/61 ad7650/52 ad7664/66 ad7653 ad7667 true bipolar ad7663 ad7665 ad7671 true differential ad7675 ad7676 ad7677 ad7621 18 bit ad7678 ad7679 ad7674 ad7641 multichannel / simultaneous ad7654 ad7655 general description the ad7654 1 i s a l o w c o s t , s i mu l t a n e o u s s a mp l i n g , d u a l - cha nnel, 16 -b i t , cha r ge r e dist r i b u t i o n sa r , a n a l o g -to - d i g i t a l co n v er t e r t h a t op era t es f r o m a s i n g le 5 v p o w e r s u p p l y . i t co n t a i n s t w o lo w n o i s e, wi de b a nd w i d t h, t r ack - a nd- h o ld a m plif iers t h a t a l lo w sim u l t an e o us s a m p ling, a h i g h sp e e d 16-b i t s a m p l i n g ad c, an in t e r n al co n v ersion c l o c k, er r o r co r r e c t i o n cir c ui ts, and b o t h s e r i a l and p a r a l l el sy stem i n ter f a c e p o r t s. e a ch t r ack-and- h o ld has a m u l t i p lexer in f r o n t t o p r o v id e a 4-c h a n ne l in p u t ad c. th e a0 m u l t i p lexer co n t r o l in p u t a l l o w s t h e c h oi c e of s i m u lt a n e o u sly s a m p l i ng i n put p a i r s in a1/inb1 (a0 = h i g h ) o r in a2/inb2 (a0 = lo w). th e p a r t f e a t ur es a v e r y hig h s a m p lin g r a t e m o de (n o r mal) a n d , f o r lo w p o w e r a p pli c a t i o n s , a r e d u ce d p o w e r m o de (i m p u l s e ) w h er e t h e p o w e r is s c a l e d wi t h t h e t h r o ug h p u t . o p era t io n is sp e c if ie d f r o m ?40c t o +85c. 1 p a te nt p e n d ing. product highlights 1. s i mu l t a n e o u s s a mp l i n g . the ad7654 f e a t ur es tw o s a m p le-an d -h ol d cir c ui ts tha t al lo w sim u l t a n eo us sam p lin g . i t p r o v ides 4- c h a n n e l in p u ts. 2. fa s t t h r o u g hp ut . the ad7654 is a 500 ks ps, c h arg e r e dis t r i b u tion, 16-b i t s a r a d c wi th i n t e rn al e r r o r c o rr ecti o n c i r c u i tr y . 3. s u p er io r inl and n o missi n g c o des. the ad7654 has a maxim u m in t e g r al n o nlinea r i ty o f 3.5 ls b wi t h n o mis s in g 16-b i t co des. 4. sing l e -su p ply op er a t ion. the ad7654 op era t es f r o m a sin g le 5 v s u p p l y . i n i m p u ls e m o de, i t s p o w e r dissi p a t io n de c r e a s e s w i t h t h r o ug h p ut. 5. se ri al o r pa r a ll e l i n t e rfa c e . v e rs a t ile p a ral l el o r 2-wir e s e r i a l in t e r f ace a r ra ng em e n t is co m p a t i b le wi th bo t h 3 v an d 5 v log i c.
ad7654 rev. a | page 2 of 28 table of contents specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 definitions of specifications ......................................................... 11 typical performance characteristics ........................................... 12 application information ................................................................ 14 circuit information .................................................................... 14 modes of operation ................................................................... 14 transfer functions ...................................................................... 14 typical connection diagram ................................................... 16 analog inputs .............................................................................. 16 input channel multiplexer ........................................................ 16 driver amplifier choice ............................................................ 16 volt age reference input ............................................................. 17 power supply ............................................................................... 17 power dissipation ....................................................................... 17 conversion control ................................................................... 18 digital interface .......................................................................... 18 parallel interface ......................................................................... 18 serial interface ............................................................................ 19 master serial interface internal clock .................................... 20 slave serial interface .................................................................. 21 microprocessor interfacing ....................................................... 23 spi interface (adsp-219x) ....................................................... 23 application hints ........................................................................... 24 layout .......................................................................................... 24 evaluating the ad7654s performance .................................... 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 11/04rev. 0 to rev. a changes to figure 7........................................................................ 12 changes to figure 18...................................................................... 15 changes to figure 19...................................................................... 16 changes to voltage reference input section............................... 17 changes to conversion control section ..................................... 18 changes to digital interface section............................................ 18 updated outline dimensions...................................................... 25 11/02revision 0: initial version
ad7654 rev. a | page 3 of 28 specifications ?40c to +85c, v ref = 2.5 v, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted. table 2. parameter conditions min typ max unit resolution 16 bits analog input voltage range v inx C v inxn 0 2 v ref v common-mode input voltage v inxn ?0.1 +0.5 v analog input cmrr f in = 100 khz 55 db input current 500 ksps throughput 45 a input impedance 1 throughput speed complete cycle in normal mode 2 s throughput rate in normal mode 0 500 ksps complete cycle in impulse mode 2.25 s throughput rate in impulse mode 0 444 ksps dc accuracy integral linearity error ?3.5 +3.5 lsb 2 no missing codes 16 bits transition noise 0.7 lsb full-scale error 3 t min to t max 0.25 0.5 % of fsr full-scale error drift 3 2 ppm/c unipolar zero error 3 t min to t max 0.25 % of fsr unipolar zero error drift 3 0.8 ppm/c power supply sensitivity avdd = 5 v 5% 0.8 lsb ac accuracy signal-to-noise f in = 20 khz 88 90 db 4 f in = 100 khz 89 db spurious-free dynamic range f in = 100 khz 105 db total harmonic distortion f in = 100 khz ?100 db signal-to-(noise + distortion) f in = 20 khz 87.5 90 db f in = 100 khz 88.5 db f in = 100 khz, ?60 db input 30 db channel-to-channel isolation f in = 100 khz ?92 db ?3 db input bandwidth 10 mhz sampling dynamics aperture delay 5 2 ns aperture delay matching 5 30 ps aperture jitter 5 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 avdd/2 v external reference current drain 500 ksps throughput 180 a digital inputs: logic levels v il ?0.3 +0.8 v v ih +2.0 ovdd + 0.3 v i il ?1 +1 a i ih ?1 +1 a
ad7654 rev. a | page 4 of 28 parameter conditions min typ max unit digital outputs data format 6 pipeline delay 7 v ol i sink = 1.6 ma 0.4 v v oh i source = ?500 a ovdd ?0.2 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 8 v operating current 9 500 ksps throughput avdd 15.5 ma dvdd 8.5 ma ovdd 100 a power dissipation 500 ksps throughput 9 120 135 mw 10 ksps throughput 10 2.6 mw 444 ksps throughput 10 114 125 mw temperature range 11 specified performance t min to t max ?40 +85 c 1 see analog inputs section. 2 lsb means least significant bi t. within the 0 v to 5 v input range, one lsb is 76.294 v. 3 see definition of specifications section. these specifications do not include the error contribution from the external referen ce. 4 all specifications in db are referred to as full-scale input fs; tested with an input signal at 0.5 db below full scale unless otherwise specified. 5 sample tested during initial release. 6 parallel or serial 16-bit. 7 conversion results are available imme diately after completed conversion. 8 the maximum should be the minimum of 5.25 v and dvdd + 0.3 v. 9 in normal mode; tested in parallel reading mode. 10 in impulse mode; tested in parallel reading mode. 11 consult sales for extended temperature range.
ad7654 rev. a | page 5 of 28 timing specifications ?40c to +85c, v ref = 2.5 v, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted. table 3. parameter symbol min typ max unit refer to figure 22 and figure 23 convert pulse width t 1 5 ns time between conversions (normal mode/impulse mode) t 2 2/2.25 s cnvst low to busy high delay t 3 32 ns busy high all modes except in master se rial read after convert mode (normal mode/impulse mode) t 4 1.75/2 s aperture delay t 5 2 ns end of conversions to busy low delay t 6 10 ns conversion time (normal mode/impulse mode) t 7 1.75/2 s acquisition time t 8 250 ns reset pulse width t 9 10 ns cnvst low to high delay t 10 30 ns eoc high for channel a conversion (normal mode/impulse mode) t 11 1/1.25 s eoc low after channel a conversion t 12 45 ns eoc high for channel b conversion t 13 0.75 s channel selection setup time t 14 250 ns channel selection hold time t 15 30 ns refer to figure 24 to figure 28 (parallel interface modes) cnvst low to data valid delay t 16 1.75/2 s data valid to busy low delay t 17 14 ns bus access request to data valid t 18 40 ns bus relinquish time t 19 5 15 ns a/ b low to data valid delay t 20 40 ns refer to figure 29 and figure 30 (master serial interface modes) cs low to sync valid delay t 21 10 ns cs low to internal sclk valid delay 1 t 22 10 ns cs low to sdout delay t 23 10 ns cnvst low to sync delay (read during convert) (normal mode/impulse mode) t 24 250/500 ns sync asserted to sclk first edge delay t 25 3 ns internal sck period 2 t 26 23 40 ns internal sclk high 2 t 27 12 ns internal sclk low 2 t 28 7 ns sdout valid setup time 2 t 29 4 ns sdout valid hold time 2 t 30 2 ns sclk last edge to sync delay 2 t 31 1 ns cs high to sync hi-z t 32 10 ns cs high to internal sclk hi-z t 33 10 ns cs high to sdout hi-z t 34 10 ns busy high in master serial read after convert 2 t 35 see table 4 cnvst low to sync asserted delay (normal mode/impulse mode) t 36 0.75/1 s sync deasserted to busy low delay t 37 25 ns
ad7654 rev. a | page 6 of 28 parameter symbol min typ max unit refer to figure 32 and figure 33 (slave serial interface modes) external sclk setup time t 38 5 ns external sclk active ed ge to sdout delay t 39 3 18 ns sdin setup time t 40 5 ns sdin hold time t 41 5 ns external sclk period t 42 25 ns external sclk high t 43 10 ns external sclk low t 44 10 ns 1 in serial interface modes, the sync, sclk, an d adout timings are defined with a maximum load c l of 10 pf; other wise c l is 60 pf maximum. 2 in serial master read during co nvert mode. see for serial master read after convert mode. table 4 table 4. serial clock timings in master read after convert divsclk[1] 0 0 1 1 divsclk[0] symbol 0 1 0 1 unit sync to sclk first edge delay minimum t 25 3 17 17 17 ns internal sclk period minimum t 26 25 50 100 200 ns internal sclk period typical t 26 40 70 140 280 ns internal sclk high minimum t 27 12 22 50 100 ns internal sclk low minimum t 28 7 21 49 99 ns sdout valid setup time minimum t 29 4 18 18 18 ns sdout valid hold time minimum t 30 2 4 30 80 ns sclk last edge to sync delay minimum t 31 1 3 30 80 ns busy high width maximum (normal) t 35 3.25 4.25 6.25 10.75 s busy high width maximum (impulse) t 35 3.5 4.5 6.5 11 s
ad7654 r e v. a | pa ge 7 o f 2 8 absolute maximum ratings table 5. p a r a m e t e r v a l u e s analog input inax 1 , inbx 1 , ref x , inxn, refgnd avdd +0.3 v to agnd ? 0.3 v ground voltage differences agnd, dgn d, ognd 0.3 v supply voltages avdd, dvdd, ovdd C0.3 v to +7 v avdd to d v dd, avdd to ovdd 7 v dvdd to ovdd C0.3 v to +7 v digital inputs C0.3 v to dv dd + 0.3 v internal power dissip a tion 2 700 mw internal power dissip a tion 3 2.5 w junction tempe r ature 150c storage temperature range C65c to +150c lead temperature range (soldering 10 sec) 300c 1 se e an alog in put s sect ion . 2 specif ication is f o r d e vice in f r ee air: 48-lead lqf p : ja = 91c/w, jc = 30c/ w. 3 speci f i c a t i o n i s fo r devi ce i n fre e a i r: 4 8 - l ea d lf cs p: ja = 26c/w. s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . to output pin c l 60pf* 500 a i oh 1.6ma i ol 1.4v *in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. 03057-002 f i gure 2 . l o a d cir c ui t fo r di g i ta l inter f a c e t i mi ng . sdout , sync, scl k o u tputs, c l = 10 pf 0.8v 2v 2v 0.8v t delay 2v 0.8v t delay 03057-003 f i gure 3. v o ltag e r e ferenc e l e vels fo r t i ming esd caution es d (e lec t r o s t a t ic dis c ha rg e) s e n s i t i v e de vic e . e l ec tr os ta tic c h a r g e s as hig h as 4 000 v r e adil y ac c u m u l a t e on t h e h u man b o dy a n d test e q ui pm e n t and can di s c ha rge w i t h o u t dete c t io n. al t h o u g h t h is p r o d u c t fe a t ur es p r o p ri e t a r y es d p r o t ecti o n ci r c ui tr y , pe rm a n en t d a ma g e ma y occur o n d e vi ces s u b j ect e d t o high en e r g y e l e c t r os t a t i c dis c ha rg es. th er efo r e , p r o p er es d p r e c a u t i o n s a r e r e co mm e nde d t o a v o i d p e r f o r ma n c e d e g r a d a t i o n or l o ss of f u nc t i on a l it y .
ad7654 r e v. a | pa ge 8 o f 2 8 pin conf iguration and fu nction descriptions 48 agnd 47 agnd 46 ina1 45 inan 44 ina2 43 re fa 42 re fb 41 inb2 40 inbn 39 inb1 38 re fgnd 37 re f 35 cnvst 34 pd 33 reset 30 eoc 31 rd 32 cs 36 dvdd 29 busy 28 d15 27 d14 25 d12 26 d13 2 avdd 3 a0 4 byteswap 7 impulse 6 dgnd 5 a/b 1 agnd 8 ser/par 9 d0 10 d1 12 d3/divsclk[1] 11 d2/divsclk[0] 13 d4/ext/int 14 d 5 /in vsyn c 15 d6 /inv s c lk 16 d7 /rdc/s d in 17 ognd 18 ovdd 19 dv dd 20 dgnd 21 d8 /s dout 22 d9 /s clk 23 d 10/syn c 24 d1 1 / rde rror pin 1 ad7654 top view (not to scale) 03057-004 f i g u re 4. 48-l e ad l qfp (st - 4 8 ) and 48 -l ead lfcs p (cp 4 8) ta ble 6. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic type 1 description 1, 47, 48 agnd p analog power g r ound pin. 2 avdd p input analog power pin. nominally 5 v. 3 a0 di m u ltiplexer sele ct. when low, the anal og inputs ina1 and inb1 are samp led sim u ltaneously, the n converted. whe n high, the analog inputs ina2 and inb2 are sampled simultan eously, then co nverted . 4 byteswap di parallel mode selection (8 bit, 16 bit). when low, the lsb is output on d[7: 0 ] and the msb is output on d[15:8]. whe n high, the lsb is output on d[1 5 :8] and the ms b is output on d[7:0]. 5 a/ b di data channel s e lection. in p a ra llel m o d e , when low, the d a ta from channe l b i s read . when high, the data from channel a is read. in serial mode, when high, channel a is output fir s t followed by channel b. when low, channel b is outp ut first followed by channel a. 6, 20 dgnd p digital power gr ound. 7 impulse di m o d e selection. when high, this input selects a reduced pow er mode. in this mode, the pow er dissipatio n is ap proxim ately pro portiona l to the samp ling rate. 8 ser/ par di serial/pa r al lel s e lection input. when low, the paral l el port is selected; when h i gh, the serial in terface mod e is sele cted and some bits of the data bus are used as a se rial port. 9, 10 d[0:1] do bit 0 and bit 1 of the parallel po rt data output bu s. when ser/ par is high, these outputs are in high impedance. 11, 12 d[2:3] or di/o when ser/ par is low, these output s are used as bit 2 and bit 3 of th e pa rallel port data output bus. divsclk[0:1] when ser/ par is high, ext/ int is low, and rdc/sdin is low, whic h i s the serial ma ster read after convert mode, these inputs, p a r t of the serial po rt, are used to slow d o wn if d e si red the internal serial clock that clocks the data outp ut. in the other serial modes, these inputs are not used. 13 d[4] di/o when ser/ par is low, this output is us ed as bit 4 of the parallel port data output bu s. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital se lect i n put for choosi n g the internal or an ex ternal da ta clock , called respectively, maste r and slave mod e . with ext / int tied low, the internal clock is sele ct ed on sclk out p ut. with ex t/ int set to a logic high, output data i s synchroni z ed to an external c l oc k si gnal connected to the sclk i n put. 14 d[5] di/o when ser/ par is low, this output is us ed as bit 5 of the parallel port data output bu s. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal in master modes. when l o w, sync is active high. when high, sync is a c tive low.
ad7654 rev. a | page 9 of 28 pin no. mnemonic type 1 description 15 d[6] di/o when ser/ par is low, this output is us ed as bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master and slave modes. 16 d[7] di/o when ser/ par is low, this output is us ed as bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an ex ternal data input or a read mode selection input, depending on the state of ext/ int . when ext/ int is high, rdc/sdin can be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on sdout with a delay of 32 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select th e read mode. when rdc/sdin is high, the previous data is output on sdout during conversion . when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground. 18 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (5 v or 3 v). 19, 36 dvdd p digital power. nominally at 5 v. 21 d[8] do when ser/ par is low, this output is us ed as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in a 32- bit on-chip register. the ad7654 provides the two conversion results, msb first, from its internal shif t register. the order of channel outputs is controlled by a/ b . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on the sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on the sclk falling edge and valid on the next rising edge. 22 d[9] di/o when ser/ par is low, this output is us ed as bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends on the logic state of the invsclk pin. 23 d[10] do when ser/ par is low, this output is us ed as bit 10 of the parallel port data output bus. or sync when ser/ par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with th e internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is lo w, sync is driven high and frames sdout. after the first channel is output, sync is pulsed low. when a read se quence is initiated and invsync is high, sync is driven low and remains low while sd out output is valid. after the first channel is output, sync is pulsed high. 24 d[11] do when ser/ par is low, this output is us ed as bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started an d not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25 to 28 d[12:15] do bit 12 to bit 15 of the parallel po rt data output bus. when ser/ par is high, these outputs are in high impedance. 29 busy do busy output. transitions high when a conversi on is started and remains high until the two conversions are complete and the da ta is latched into the on-chip sh ift register. the falling edge of busy can be used as a data ready clock signal. 30 eoc do end of convert output. goes low at each channel conversion. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the ex ternal serial clock. 33 reset di reset input. when set to a logic high, reset the ad7654. current conversion if any is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high, pow er consumption is reduced and conversions are inhibited after the current one is completed.
ad7654 rev. a | page 10 of 28 pin no. mnemonic type 1 description 35 cnvst di start conversion. a falling edge on cnvst puts the internal sample-and-hold into the hold state and initiates a conversion. in impulse mode (impulse = high), if cnvst is held low when the acquisition phase (t 8 ) is complete, the internal sample-and-hold is put into the hold state and a conversion is immediately started. 37 ref ai this input pin is used to provide a reference to the converter. 38 refgnd ai reference input analog ground. 39, 41 inb1, inb2 ai channel b analog inputs. 40, 45 inbn, inan ai analog inputs ground senses . allow to sense each channel ground independently. 42, 43 refb, refa ai these inputs are the referenc es applied to channel a and channel b, respectively. 44, 46 ina2, ina1 ai channel a analog inputs. 1 ai = analog input; di = digital input; di/o = bidirectional digital; do = digital output; p = power.
ad7654 rev. a | page 11 of 28 definitions of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last co de transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 111. . .10 to 111. . .11) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (4.999886 v for the 0 v to 5 v range). the full-scale error is t he deviation of the actual level of the last transition from th e ideal level. unipolar zero error in unipolar mode, the first transition should occur at a level 1/2 lsb above analog ground. the unipolar zero error is the deviation of the actual transition from that point. spurious-free dynamic range (sfdr) the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to sinad by the following formula: enob = ((sinad db ? 1.76) /6.02) and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. aperture delay aperture delay is a measure of acquisition performance and is measured from the falling edge of the cnvst input to when the input signals are held for a conversion. transient resp onse the time required for the ad7654 to achieve its rated accuracy after a full-scale step function is applied to its input.
ad7654 rev. a | page 12 of 28 typical perf orm ance cha r acte ristics code ?1 inl ( l sb) ?5 ?3 65535 0 ?2 ?4 32768 16384 49152 0 1 2 3 4 5 03057-005 f i gure 5 . integr a l no nli n ea ri t y vs . c o d e code in hex 7fbf 0 counts 8000 6000 4000 2000 0 7000 3000 1000 5000 7fc0 0 7fc1 14 7fc2 953 7fc3 7288 7fc4 7220 7fc5 903 7fc6 6 7fc7 0 7fc8 0 03057-006 f i g u re 6. his t og r a m of 1 6 ,3 8 4 conver s i ons of a dc input at t h e code t r ans i t i on frequency (khz) ?120 amp l itude (db of full s c a l e ) ?160 150 0 ?140 100 50 125 ? 100 ?8 0 ?6 0 ?40 ?20 0 25 75 175 200 225 250 8192 point fft f s = 500khz f in = 100khz, ?0.5db snr = 89.9db sinad = 89.4db thd = ? 99.3db 03057-007 f i g u re 7. fft plot code dnl (ls b ) ?3 0 ?2 16384 32768 ?1 0 1 2 3 49152 65535 03057-008 f i gur e 8 . d i ffe r e ntia l no nl inea ri t y vs . c o de code in hex 8000 7fc0 0 counts 7000 4000 2000 0 6000 3000 1000 5000 7fc1 7fc2 7fc3 176 7fc4 7fc5 132 7fc6 7fc7 00 7fbf 0 9366 9000 10000 3411 3299 03057-009 f i g u re 9. his t og r a m of 1 6 ,3 8 4 conver s i ons of a dc input at t h e cod e c e n t er temperature ( c) 96 s nr (db) 84 90 25 125 ?55 93 87 ?3 5 6 5 45 5 105 ?15 8 5 ?9 8 thd (db) ? 106 ? 102 ? 100 ? 104 snr thd 03057-010 f i gure 10. snr , t h d v s . t e mper ature
ad7654 rev. a | page 13 of 28 frequency (khz) 100 s nr, s i nad (db) 90 70 80 10 1000 1 100 95 85 75 16.0 enob ( b it s) 15.0 13.0 14.0 15.5 14.5 13.5 snr sinad enob 03057-011 f i gure 11. snr, si n a d , and eno b vs. f r equ e nc y input level (db) 92 s nr, s i nad (db) 90 86 88 ?40 ? 20 ?6 0 ? 3 0 ? 5 0 ? 10 0 snr sinad 03057-012 f i gure 12. snr and sinad vs . input l e v e l (referred to f u ll s c ale) frequency (khz) thd, harmonics , cros s t alk (db) ?115 ?105 10 1000 1 100 ? 110 90 s f dr (db) 80 60 70 85 75 65 ? 100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 95 100 105 110 115 sfdr crosstalk b to a crosstalk a to b thd third harmonic second harmonic 03057-013 f i gur e 1 3 . th d , ha rm oni c s , cr o sstal k , a n d sfdr vs . f r e q ue nc y temperature ( c) lsb ?10 ?1 5 ?55 2 5 ?3 5 5 4 5 ?8 ?6 ?4 ?2 0 2 4 6 8 10 65 85 105 125 full-scale error zero error 03057-014 f i gure 14. f u ll s c al e and zero e r r o r v s . t e mpe r atu r e op e rating curre nts (ma) 10 1 0.1 100 sampling rate (ksps) 10 100 1000 1 normal avdd normal dvdd impulse avdd ovdd 2.7v 0.01 0.001 0.0001 impulse dvdd 03057-015 f i gure 15. o p er atin g currents v s . s a m p le r a te c l (pf) 50 t 12 de lay (ns ) 20 0 10 100 200 0 150 50 30 40 ovdd = 2.7v @ 85 c ovdd = 2.7v @ 25 c ovdd = 5v @ 85 c ovdd = 5v @ 25 c 03057-016 f i g u re 16. t y pic a l d e lay v s . l oad cap a c i t a nce c l
ad7654 rev. a | page 14 of 28 application information circuit information the ad7654 is a v e r y fas t , lo w p o w e r , sin g l e -s u p p l y , p r ecis e s i mu l t a n e o u s s a mp l i n g 1 6 - b i t a n a l o g - t o - d i g i t a l c o n v e r t e r (ad c ). the ad7654 p r o v ides t h e us er wi th tw o o n -c hi p trac k-an d- h o ld , suc c essi ve a p p r o x ima t io n ad cs t h a t do no t ex hib i t an y pi p e l i ne or l a te nc y , m a k i ng i t i d e a l for m u lt i p l e m u lt i p l e x e d c h a nne l a p p l ic a t io n s . th e ad7 654 ca n als o be us ed as a 4-c h a n n e l ad c wi th tw o p a irs sim u l t an e o us l y s a m p le d . the ad7654 can b e o p era t ed f r o m a sing le 5 v s u p p l y a nd be in t e r f aced t o ei t h er 5 v o r 3 v dig i tal log i c. i t is h o us e d in 48-lead l q fp o r tin y 48-lead l f cs p p a cka g es t h a t com b i n e sp ace s a v i n g s and a l lo w f l exi b l e co nf igura t io n s as ei t h er a s e r i a l o r p a ral l e l in t e r f ace . the ad76 54 is p i n-t o -p in co m p a t i b le wi th pu lsar ad cs . modes of operation the ad7654 f e a t ur es tw o m o des o f o p era t io n, n o r m al an d i m p u ls e. e a c h of th es e m o des is m o r e s u i t a b l e f o r s p ecif ic ap p l i c at i o n s . the n o r m al mo de is t h e fas t est m o de (500 ks ps). e x cep t w h en i t is p o w e r e d d o w n (pd = hi g h ), t h e p o w e r d i ssi p a t ion is alm o st in dep e nden t o f t h e s a m p lin g ra te . the i m p u ls e mo de, t h e lo w e st p o w e r diss i p a t i o n mo de, a l lo w s p o w e r sa vi n g b e t w een co n v ersi o n s. th e max i m u m t h r o ug h p u t in t h is mo d e i s 44 4 ksps . w h en o p era t in g a t 10 ks ps, f o r exa m p l e , i t typ i cal l y co n s um es only 2.6 mw . this f e a t u r e mak e s t h e ad7654 ide a l f o r b a t t e r y - p o w er e d a ppl i c at i o ns . trans f er functi ons the ad7654 da ta f o r m a t is s t raig h t b i na r y . the ideal tra n sf er c h a r ac t e r i s t ic f o r th e ad7654 is s h o w n in f i gur e 17 a nd t a b l e 7 . the ls b size is 2*v ref /65536, w h ic h is abo u t 76.3 v . 000...000 000...001 000...010 111...101 111...110 111...111 analog input +fs ? 1.5 lsb +fs ? 1 lsb ?fs + 1 lsb ?fs ? fs + 0.5 lsb adc code (s tra i ght bina ry ) 03057-017 f i g u re 17. a d c ide a l t r ans f er f u nc t i o n ta ble 7. out p ut codes a n d i d ea l input volt a g es description analo g input v re f = 2.5 v digital o u tput co de fsr ? 1 lsb 4.999924 v 0xffff 1 fsr ? 2 lsb 4.999847 v 0xfffe midscale + 1 lsb 2.500076 v 0x8001 midscale 2.5 v 0x8000 midscale ? 1 lsb 2.499924 v 0x7fff ?fsr + 1 lsb ?76.29 v 0x0001 ?fsr 0 v 0x0000 2 1 t h is is al so the c o de f o r ov er range anal og input ( v C v a b o v e 2 ( v - v )). in x in xn re f re f g nd 2 this is al so the c o de fo r underrange analog input (v in x be low v in xn ).
ad7654 rev. a | page 15 of 28 avdd agnd dgnd dvdd ovdd ognd ser/par cnvst busy sdout sclk rd cs reset pd refgnd c ref 2.5v ref note 1 ref ref a ref b 30 ? d clock ad7654 c/ p/ dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd a/b note 7 byteswap dvdd 50k ? 100nf 1m ? ina1 c c 2.7nf u1 note 4 note 5 50 ? - + 15 ? 2.7nf u2 note 4 note 5 50 ? - + 15 ? inan ina2 note 2 note 3 note 6 ad780 10 f 100nf + 100nf + 100nf + 10 f 50 ? + notes 1. see voltage reference input section. 2. with the recommended voltage references, c ref is 47 f. see voltage reference input section. 3. optional circuitry for hardware gain calibration. 4. the ad8021 is recommended. see driver amplifier choice section. 5. see analog inputs section. 6. optional, see power supply section. 7. optional low jitter cnvst. see conversion control section. a0 inb1 2.7nf u3 note 4 note 5 50 ? - + 15 ? inbn 2.7nf u4 note 4 note 5 50 ? - + 15 ? inb2 analog input a1 analog input a2 analog input b1 a nalog input b2 c c c c c c 10 f 1 f 03057- 019 note 1 f i g u re 18. t y pic a l conne c t io n d i ag r a m ( s er ia l int e r f ac e)
ad7654 rev. a | page 16 of 28 typical connection diagram f i gur e 18 sh o w s a typ i cal co nn e c tio n dia g ra m fo r th e ad7654. d i f f e r e n t c i rc u i t r y sho w n on t h i s d i ag r a m i s opt i on a l a n d i s d i scu s se d be l o w . analog inputs fi g u r e 1 9 s h ow s a s i m p l i f i e d a n a l o g i n pu t s e c t i o n o f t h e ad7654. ina1 r a inb2 c s c s agnd avdd ina2 inan inbn inb1 r b 03057-018 a0 a0 = l a0 = l a0 = h a0 = h f i g u re 19. si mpl i f i e d a n al og input the dio d es sh o w n i n f i gur e 19 p r o v ide es d p r o t e c t i o n fo r t h e in p u ts. c a r e m u s t b e tak e n t o en s u r e tha t t h e analog in p u t sig n al ne v e r exc e e d s the a b s o l u te ra tin g s on t h e s e in p u ts. this ca us es t h es e di o d es to b e co me fo r w a r d b i a s e d and st a r t co nd uc t i ng c u r r en t. t h es e dio d es ca n hand le a fo r w a r d-b i a s e d c u r r en t o f 120 ma maxim u m. this con d i t ion co u l d ev en t u al ly o c c u r w h en t h e in p u t b u f f er s (u1) o r (u2) s u p p lies a r e d i ff e r e n t fr o m a v d d . i n s u c h c a s e , a n i n p u t b u ff e r w i t h a sh o r t-c i r c ui t c u r r en t limi t a t i o n ca n b e us e d t o pr o t e c t t h e p a r t . this a n alog i n pu t s t r u c t ur e al lo ws t h e s a m p lin g o f t h e dif f er en t i a l sig n a l b e tw e e n in x a nd in x n . u n li k e o t her co n v er t e rs, t h e i n xn is s a m p le d a t t h e s a m e t i me as t h e in x in p u t. by usin g t h es e dif f er en t i a l in p u ts, smal l si g n als co mm on t o bo t h in p u ts ar e r e jec t ed. dur i n g t h e ac q u isi t io n p h as e , f o r ac sig n als, the ad7654 b e h a v e s lik e a o n e- po l e r c f i l t er co n s i s t e d o f t h e eq ui val e n t re s i st anc e r a , r b , a nd c s . th e resis t o r s r a and r b are t y pi c a l l y 500 ? a n d a r e a l u m p e d co m p on en t made u p of s o m e s e r i al r e sis t o r s a n d t h e o n r e sis t an ce o f t h e s w i t ch es. the c a p a ci t o r c s is ty p i c a l l y 32 pf a n d is m a in ly t h e ad c s a m p l i n g c a p a ci t o r . this on e-p o le f i l t er wi t h a typ i c a l ?3 db c u t o f f f r eq uen c y o f 10 mh z r e d u ce s undesira b l e al i a sin g ef fe c t a nd limi ts t h e n o is e co min g f r o m t h e in p u ts. s i nce t h e in p u t im p e dan c e o f t h e ad7654 is ver y hig h , t h e ad7654 can be dr i v en dir e c t l y b y a lo w im p e da n c e s o ur ce wi t h o u t ga i n er r o r . t o f u r t h e r im p r o v e t h e n o is e f i l t er in g o f t h e ad7654 a n alog in p u t cir c ui t, an ext e r n al o n e-p o le r c f i l t er b e tw e e n t h e am plif ier o u t p u t and t h e ad c i n pu t as sh o w n i n f i gur e 18 can b e us ed . h o w e v e r , th e s o ur ce im p e dan c e has t o be k e p t lo w b e ca us e i t a f fe c t s t h e ac p e r f o r ma n c e , es p e c i al l y t h e tot a l h a r m on i c d i stor t i on . t h e m a x i m u m s o u r c e i m p e d a nc e d e p e nd s o n t h e amou n t of tot a l h a r m on i c d i stor t i on ( t h d ) th a t ca n be t o le ra t e d . th e t h d d e gra d e s wi th in cr ea s e o f th e s o ur ce i m p e dance. input channel multiplexer the ad7654 al lo ws t h e ch o i ce o f sim u l t an eo usl y s a m p lin g t h e in p u ts p a irs in a1/inb1 o r in a2/inb2 wi t h t h e a0 m u l t i p lexer in p u t. w h en a0 is lo w , t h e in p u t p a irs in a1 /in b 1 a r e s e le c t e d a nd w h e n a0 is hig h t h e i n p u t p a irs in a2 /inb2 a r e s e le c t e d . n o t e t h a t i n ax is al wa ys con v er t e d bef o r e inbx r e ga r d les s o f t h e st a t e o f t h e dig i t a l i n ter f ace cha nnel s e le c t i o n a/ b pi n . i t s h o u l d be n o t e d tha t t h e c h a n n e l s e le c t ion co n t rol a0 s h o u l d n o t b e chan ge d d u r i n g t h e acq u isi t io n phas e o f t h e co n v er t e r . driver am plifier ch o i ce al t h o u g h t h e ad7654 is easy t o dr i v e , t h e dr i v er a m p l if ier n eed s t o m e e t a t l e a s t t h e f o ll o w in g r e q u i r em en t s : ? the dr i v er am p l if ier a nd t h e ad7654 a n alog in p u t c i r c ui t to ge t h e r m u st b e abl e to s e tt l e for a f u l l - s c a l e s t e p of t h e ca p a ci t o r a r ra y a t a 16 -b i t leve l (0.0015%). i n t h e am p l if ier s da ta sh eet, t h e s e t t l i n g a t 0.1 % o r 0.01% is m o r e co mm onl y sp e c if ie d . i t co u l d sig n if ican t l y dif f er f r o m t h e s e t t ling t i m e a t a 16 -b i t le ve l a n d , t h er ef o r e , i t sh o u ld be v e r i f i e d p r io r t o th e dr i v er s e lec t io n. th e tin y o p a m p ad8021, which co m b i n es u l t r a l o w n o is e and a hig h gain b a ndwi d t h , m e et s th i s set t li n g tim e r e q u i r em e n t e v e n w h en used w i th a h i g h ga in o f u p t o 13. ? the n o is e g e n e r a t e d b y t h e dr i v er a m plif ier n e e d s t o b e kep t as lo w as p o s s i b le t o p r es er v e t h e s n r and t r a n s i t i o n n o is e p e r f o r ma n c e o f th e ad7654. the n o is e co min g f r o m th e dr i v er is f i l t er ed b y t h e ad7654 a n alog in p u t cir c ui t o n e- p o le lo w-p a s s f i l t er made b y r a , r b , a nd c s . th e s n r deg r a d a t io n d u e t o t h e a m pl if ie r is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 3 2 ) ( 2 56 56 log 20 n db loss ne f snr w h er e: f C3 db is th e C3 db in p u t ban d wid t h in m h z o f th e ad7654 ( 1 0 m h z ) o r t h e c u t o ff fr e q u e n c y o f t h e i n p u t fi l t e r i f a n y i s us ed . n is t h e n o is e f a c t o r o f t h e am pl if ier (1 if in b u f f er co nf igura t io n). e n is t h e e q ui v a l e n t i n p u t n o is e v o l t a g e o f t h e op am p i n n v / hz . f o r in st an ce , a dr i v er w i t h a n e q ui va le n t in pu t n o is e o f 2 nv/ h z li k e t h e ad8021 an d co nf igur ed as a b u f f er , th us wi t h a n o is e ga i n o f +1, deg r ades t h e s n r b y o n l y 0 . 03 db wi t h t h e f i l t er in f i gur e 18, a nd 0.09 db wi t h o u t.
ad7654 rev. a | page 17 of 28 ? the dr i v er n e e d s t o ha v e a th d p e r f o r ma n c e s u i t ab le t o tha t o f t h e ad7 654. the ad8021 meets t h es e r e q u ir em en ts and is us ual l y a p p r o p r i a t e f o r alm o st al l a p p l ica t io ns. th e ad8021 n e e d s a n ext e r n al co m p en s a tion c a p a ci to r o f 10 p f . this ca p a ci t o r sh o u ld ha ve go o d li n e ar i t y as a n npo cera mic o r mic a ty p e . t h e ad8022 co u l d be us e d w h er e a d u a l v e rsio n is n e e d ed and a ga in o f +1 is us e d . the ad829 is an o t h e r al t e r n a t iv e w h er e hig h f r eq uen c y (a b o v e 100 kh z) p e r f o r ma n c e is n o t r e q u ir ed . i n a ga in o f +1, i t r e q u ir es a n 82 p f co m p en s a tion ca p a ci t o r . the ad8610 is a n o t h e r o p t i o n wher e lo w b i as c u r r en t is neede d in lo w f r e q uen c y a p plica t io n s . voltage r e ference input the ad7654 r e q u ir es a n ext e r n al 2.5 v r e f e r e nce . th e r e f e r e n c e in p u t sh o u ld b e a p plie d t o ref , ref a , a nd ref b . th e v o l t a g e r e f e r e n c e in p u t ref o f th e ad7 654 has a d y namic in p u t im p e dan c e; i t sh o u ld t h er efo r e b e dr i v en b y a l o w i m p e dan c e s o ur ce wi t h a n ef f i cien t deco u p lin g . this deco u p lin g dep e n d s o n t h e ch o i ce o f t h e v o l t a g e r e fe r e n c e b u t usual l y co n s is ts o f a 1 f cera mic ca p a ci t o r a nd a lo w es r tan t al u m ca p a ci t o r co nn e c te d to t h e ref a , ref b , a nd ref g n d i n p u ts w i t h minim u m p a rasi tic ind u c t an c e . 47 f is a n a p p r o p r i a t e val u e f o r th e ta n t al um ca pa ci t o r w h e n usi n g o n e o f th e r e co mm en ded re f e re nc e vo lt ag e s : ? the lo w n o is e , l o w t e m p era t ur e dr if t ad780 v o l t a g e re f e re nc e ? the lo w cos t ad1582 v o l t a g e ref e r e n c e f o r a p p l ica t ion s usin g m u l t i p le ad7654s wi t h on e v o l t a g e re f e re nc e s o u r c e , it i s re c o m m e n d e d t h a t t h e re f e re nc e s o u r c e dr i v es e a ch ad c in a s t a r conf igura t io n w i t h i n d i vi d u a l de co u p ling plac e d as clos e as p o ssi b le t o t h e r e f/refgnd in p u ts. als o , i t is r e co mm e nde d t h a t a b u f f er , s u c h as t h e ad8031/32 , b e us e d i n t h is co n f igura t io n. c a r e sh o u ld b e t a k e n w i t h t h e refer e n c e t e m p er a t ur e co ef f i cien t of t h e vo lt age re f e re nc e, w h i c h d i re c t ly af f e c t s t h e f u l l - s c a l e acc u rac y if t h is p a ra m e t e r is a pplica b le. f o r in st a n c e , a 15 p p m /c t e m p co o f th e r e f e r e n c e c h a n g e s t h e f u l l -s cale acc u rac y b y 1 ls b/c. power supply the ad7654 us es thr e e s e ts o f p o w e r s u p p l y p i n s : a n a n alog 5 v su p p ly a v dd , a dig i t a l 5 v c o re su p p ly d v dd , and a dig i t a l in p u t/out p ut i n te r f ac e su p p ly o v dd . t h e o v dd su p p ly a l l o ws dir e c t in ter f ace wi th an y log i c w o rkin g betw een 2.7 v an d d v d d + 0.3 v . t o r e d u ce t h e n u m b er o f s u p p li es n e e d e d , t h e dig i t a l co r e (d v d d) ca n b e su pplie d t h r o ug h a sim p le rc f i l t er f r o m th e a n alog s u p p l y , as sh o w n in f i gur e 18. the ad7654 is inde p e n d e n t o f p o w e r su p p ly s e q u en c i ng, o n ce o v dd do es n o t e x ceed d v d d b y m o r e th a n 0.3 v , a n d t h us f r ee f r o m s u p p l y v o l t a g e in d u ce d la t c h - u p . a d di t i o n all y , i t i s v e r y i n sen s i t i v e t o p o we r supply v a r i a t i o ns o v e r a w i d e f r e q u e nc y r a nge, a s s h ow n in f i gur e 20. frequency (khz) 40 p s rr (db) 100 1000 10000 45 50 55 60 65 70 10 1 03057-020 fi g u r e 2 0 . p s r r v s . fr e q u e n c y power diss ipatio n i n i m p u ls e mo de , t h e ad7654 a u t o ma tical l y r e d u ces i t s p o wer co n s um p t io n a t t h e e nd o f e a ch co n v ersio n pha s e. d u r i ng t h e acq u isi t ion phas e , t h e op era t ing c u r r en ts a r e ver y lo w , w h ich al lo ws sig n if i c an t p o w e r s a vi n g s w h en t h e co n versio n ra t e is r e d u ced , as sh o w n in f i gur e 21 . this f e a t ur e mak e s t h e ad765 4 ide a l fo r v e r y lo w p o w e r b a t t e r y a p plic a t io n s . i t s h o u ld b e n o t e d t h a t th e d i gi ta l i n t e rf a c e r e m a i n s a c ti v e e v e n d u r i n g t h e acq u isi t io n phas e . t o r e d u ce t h e o p era t in g dig i t a l s u p p l y c u r r en ts e v en f u r t h e r , t h e dig i t a l in pu ts n e e d t o b e dr i v en clo s e to t h e p o w e r r a i l s (i.e., d v dd an d d g nd), and o v d d sh o u ld n o t excee d d v d d b y m o r e than 0.3 v . sampling rate (ksps) 0.1 pow e r d i ssipa tion ( m w ) 100 1000 1 10 100 1000 normal impulse 03057-021 10 1 f i g u re 21. p o wer d i s s i pat i o n v s . s a mp l e ra te
ad7654 rev. a | page 18 of 28 conversion control f i gur e 22 s h o w s th e de ta iled ti mi n g di a g ra m s o f th e co n v ersio n p r o c es s. th e ad76 54 is co n t r o l l ed b y t h e sig n al cnv s t , w h ich in i t ia t e s con v ersion. o n ce i n i t i a t e d , i t c a n n ot b e re st ar te d or a b or te d, e v e n b y t h e p o w e r - d o w n i n put , p d , un til t h e con v ersio n is com p let e . th e cnv s t sig n al o p era t es i n de p e n d en t l y o f t h e cs a nd rd sig n als. busy acquire t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 convert a acquire convert convert b t 12 a0 t 14 t 15 t 13 t 11 t 10 eoc cnvst 03057-022 mode f i gure 22. bas i c co n v ersi on ti ming al t h o u g h cnv s t i s a di gi tal si gn al , i t s h o u l d be d e s i g n ed w i th sp e c ia l ca r e w i t h fast , cle a n e d ges a nd le vels, a nd w i t h mi ni m u m o v e r s h o o t a n d u n d e r s ho ot or r i ng i n g . f o r a p plica t ion s w h er e t h e snr is cr i t ica l , t h e cnv s t sig n al s h o u l d ha ve v e r y lo w ji t t er . s o me s o l u tio n s t o achiev e this a r e t o us e a de dic a te d o s ci l l a t o r fo r cnv s t ge ne r a t i on or , at l e a s t , to clo c k i t w i t h a h i g h f r e q ue n c y lo w j i t t e r clo c k, as sho w n in f i gur e 18. i n i m p u ls e mo de , co n v ersion s c a n b e a u t o ma t i c a l l y ini t ia t e d. i f cnv s t is he ld lo w w h en b u s y is lo w , t h e ad7654 co n t r o ls th e acq u isi t ion pha s e an d a u t o m a t i ca l l y ini t i a t e s a ne w con v ersio n . by ke ep ing cnv s t lo w , th e ad7654 k e eps the co n v ersio n p r o c ess r u nning b y i t s e lf. i t sh ou ld b e n o te d t h a t t h e a n a l o g i n put h a s to b e s e tt l e d w h e n bu s y go e s l o w . a l s o , a t p o we r - up , cnv s t shou l d b e brou g h t l o w onc e to i n it i a te t h e c o n v e r s i on p r o c es s. i n this m o de , t h e ad7 654 co u l d s o m e tim e s r u n sl ig h t ly f a ste r t h an t h e g u ar an te e d l i m i ts in t h e i m p u l s e mo de of 444 ks ps. this f e a t ur e do es n o t exis t in n o r m al m o de . digi tal in t e rface the ad7654 has a v e rs a t ile dig i tal in t e r f ace; i t c a n b e in t e r f ace d wi th t h e h o st sys t em b y usin g ei th er a s e r i al o r p a ral l e l in t e r f ac e . the s e r i al i n ter f ace is m u l t i p lexe d o n t h e p a ral l e l da t a b u s. th e ad7654 dig i t a l in t e r f ace accomm o d a t es ei t h er 3 v o r 5 v log i c b y sim p l y co nnec tin g t h e o v dd s u p p l y p i n o f th e ad7654 t o t h e ho st s y s t e m in te r f ac e d i g i t a l su p p ly . the tw o sig n als cs a nd rd co n t r o l t h e in t e r f ace. w h en a t l e ast o n e o f t h es e s i g n als is hig h , t h e in t e r f ace o u t p u t s a r e in hig h i m pe da nce . u s u a ll y , cs al lo ws t h e se l e c t io n o f e a ch ad76 54 in m u lt ic ir c u i t a ppli c a t i o ns and is held l o w in a s i ng l e ad765 4 desig n . rd is g e n e r a l l y us ed t o enab le t h e con v ersio n r e s u l t o n th e da t a b u s. i n p a ral l e l m o de , s i g n al a/ b al lo ws th e ch o i ce o f r e ading ei t h er t h e o u t p ut o f c h a nne l a o r c hanne l b , w h er e a s in ser i al m o de , signal a/ b co n t r o ls w h ich cha n ne l is o u t p u t f i rst. f i gur e 23 det a ils t h e t i min g w h en usin g t h e res e t i n p u t. n o t e t h e c u r r en t con v ersio n , if an y , i s a b o r t e d and t h e da t a b u s is hig h im p e dan c e w h i l e reset is hig h . t 9 reset data bus busy t 8 cnvst 03057-023 f i g u re 23. r e s e t ti ming parallel interf ace the ad7654 is co nf igur ed t o us e t h e p a ral l e l in t e r f ac e w h en se r / pa r is h e l d lo w . master pa rall el int e rf ac e d a t a can b e r e a d co n t in uo usly b y ty in g cs a nd rd lo w , t h us r e q u ir in g m i n i ma l micr o p r o ce ss o r co nne c t io ns. h o w e ver , in t h is mo de t h e d a t a b u s is a l w a y s dr i v en and cann ot b e us e d in s h a r e d b u s ap p l i c at i o n s ( u n l e s s t h e d e v i c e i s h e l d i n r e s e t ) . f i gur e 24 d e t a ils th e ti mi n g f o r th i s m o d e . t 1 t 3 t 4 t 17 busy data bus t 16 new a or b previous channel a or b previous channel b or new a t 10 cs = rd = 0 eoc cnvst 03057-024 f i g u re 24. m a s t e r p a r a l l e l d a t a tim i ng f o r r e adi n g (cont i nuous r e ad)
ad7654 rev. a | page 19 of 28 slave p a rallel interface i n sla ve p a ral l e l re adi n g m o de , t h e da t a can b e r e ad ei t h er a f t e r e a ch con v ersio n , w h ich is d u r i ng t h e next acq u i s i t io n phas e o r d u r i ng t h e ot he r ch an n e l s c o n v e r s i on , or d u r i n g t h e f o l l o w i n g c o n v e r s i on a s s h ow n i n f i g u re 2 5 an d f i g u re 2 6 re sp e c t i v e ly . w h en t h e da t a i s r e ad d u r i n g t h e co n v ersion, ho w e v e r , i t is r e co mm e nde d t h a t i t is r e ad o n ly d u r i n g t h e f i rst half o f t h e c o n v e r s i on ph a s e. t h i s a v oi d s a n y p o te n t i a l f e e d t h rou g h b e tw e e n v o l t a g e t r a n sien ts on t h e dig i t a l in ter f ace an d t h e m o s t cri t i c al a n alog co n v er si o n ci r c ui tr y . data bus t 18 t 19 busy current conversion cs rd 03057-025 f i gure 25. sl ave p a r a l l e l d a ta tim i ng f o r r e adi n g (r ead a f ter co n v e r t) previous conversion t 1 t 3 t 18 t 19 t 4 busy data bus t 13 t 11 t 12 t 10 cs = 0 eoc cnvst, rd 03057-026 f i gure 26. sl ave p a r a l l e l d a ta tim i ng f o r r e adi n g (r ead d u ring con v e r t) 8-bit interface (master or sl ave) the by tesw a p p i n a l lo ws a g l ueless i n ter f ac e to a n 8- b i t b u s. a s sho w n in f i g u r e 27, th e ls b b y t e is o u t p u t o n d[7:0] a nd t h e ms b is o u t p u t on d[15:8] w h en by tesw ap is lo w . w h en by tesw ap is hig h , t h e ls b and ms b b y t e s ar e swa p p e d , t h e ls b is o u t p u t on d[15:8], a nd t h e ms b is ou t p u t o n d[7:0]. b y co nn e c t i n g b y tesw ap to a n addr ess l i n e , t h e 16-b i t da t a can be r e ad in tw o b y t e s o n ei t h er d[15:8] o r d[7:0 ] . byteswap pins d[15:8] pins d[7:0] hi-z hi-z high byte low byte low byte high byte hi-z hi-z t 18 t 18 t 19 cs rd 03057-027 f i g u re 27. 8-b i t p a r a l l e l int e r f a c e cha n nel a/ b ou tpu t the a/ b in p u t con t r o ls whic h c h a nne l s con v ersio n r e s u l t s (in a x o r inbx) wi ll be o u t p u t o n th e d a t a b u s . th e fun c tio n ali t y of a / b is detailed in f i gur e 28. w h en hig h , t h e da ta f r o m c h a nne l a is a v a i la b l e o n t h e da t a b u s. w h e n l o w , t h e da t a f r o m c h a nnel b is a v a i la b l e o n t h e b u s. n o te t h a t c h a nnel a can b e r e ad imme di a t el y a f t e r co n v ersi o n is don e ( eo c ), while c h a nne l b is sti l l in i t s con v er tin g p h as e . t 18 t 20 cs data bu s rd hi-z a/b hi-z channel a channel b 03057- 028 f i g u re 28. a / b chan nel r e ad ing serial interface the ad7654 is co nf igur ed t o us e t h e s e r i al in t e r f ace w h en t h e se r / pa r is h e l d hig h . th e ad7654 o u t p u t s 32 b i ts o f da t a , m s b f i r s t , on t h e sd ou t pi n . t h e ord e r of t h e ch an nel s b e i n g o u t p u t is als o co n t r o l l ed b y a/ b . w h en hig h , c h a nne l a is o u t p u t f i rs t; w h en lo w , c h a n ne l b is o u t p u t f i rs t. u n li k e in p a r a l l el m o de, c h a nnel a da t a is u p da te d o n ly a f ter c h a nnel b co n v ersio n . thi s da t a is sy n c hr o n ize d wi t h t h e 32 clo c k p u ls es p r o v i d ed o n t h e sc l k p i n .
ad7654 rev. a | page 20 of 28 master serial interface inter n al cloc k the ad7654 is co nf igur ed t o g e n e ra t e and p r o v ide t h e s e r i a l da ta c l o c k scl k w h en t h e ext/ int p i n is he ld lo w . the ad7654 als o g e n e ra t e s a s y nc sig n al t o indic a te t o the h o s t w h en t h e s e r i al da t a is vali d . the s e r i al clo c k s c lk and t h e s y n c s i g n a l can b e i n ver t e d if desir e d . the o u tp u t da t a is va lid o n b o th th e ri s i n g a n d f a lli n g ed g e o f t h e d a ta c l oc k . d e pe n d i n g o n rd c / s d in in p u t, t h e da ta c a n b e r e ad a f t e r eac h con v ersio n o r du r i n g t h e f o l l ow i n g c o n v e r s i o n . fi g u r e 2 9 a n d fi g u r e 3 0 s h o w t h e d e ta ile d ti mi n g di a g ra m s o f th ese t w o m o d e s. u s ual l y , be ca us e the ad7654 is us ed wi t h a fas t thr o ug h p u t , t h e m a ster - r e a d - d u r i n g - c o n ver t m o de is t h e m o st r e co m m e n de d s e r i a l mo de w h en i t can b e us e d . i n t h is m o de, t h e s e r i a l clo c k a nd da t a to g g l e a t a p p r o p r i a t e i n st an ts, w h ich mini mi ze po t e n t ial f eed thr o ugh b e tw ee n d i gi tal a c t i vi t y a n d t h e cri t ical co n v ersio n de cisio n s. th e s y nc sig n al g o es lo w a f t e r t h e ls b o f ea c h c h a n n e l h a s been o u t p u t . n o t e th a t i n thi s m o d e , t h e sclk p e r i o d c h a n g e s since t h e ls bs r e q u ir e mo r e time t o s e t t le , and t h e s c lk is der i v e d f r o m t h e sa r c o n v ersio n clo c k. i n m a s t er - r e a d-af t e r - c o n v er t m o de , i t sh o u l d b e n o t e d t h a t u n l i ke i n ot he r mo d e s , t h e s i g n a l b u sy re t u r n s l o w af te r t h e 32 da t a b i ts a r e p u ls e d o u t and n o t a t t h e e nd of t h e con v ersion phas e , w h ich r e s u l t s i n a lo n g er b u s y w i d t h. o n e ad van t a g e o f t h is mo de is t h a t i t c a n accom m o d a t e slo w dig i t a l h o sts b e ca us e th e s e r i al c l o c k ca n be s l o w e d do wn b y usin g d i v s clk. t 3 busy sync sclk sdout 1 2 16 30 31 32 ch a d15 ch a d14 ch b d2 ch b d1 ch b d0 x rdc/sdin = 0 invsclk = invsync = 0 t 21 t 27 t 22 t 23 t 29 t 30 t 36 t 25 t 28 t 37 t 32 t 31 t 33 t 34 t 12 t 13 17 t 35 t 26 ext/int = 0 a/b = 1 cnvst cs, rd eoc 03057- 029 f i gure 29. mas t e r s e ri al d a ta tim i ng f o r r e adi n g (r ead a f ter co n v e r t) rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 24 t 21 t 26 t 27 t 28 t 31 t 33 t 32 t 34 t 30 t 29 t 23 t 22 ch a d15 x 12 16 1 2 t 25 busy sync sclk sdout 16 ch b d15 ch a d0 ch a d14 ch b d14 ch b d0 t 10 t 11 t 13 t 12 ext/int = 0 a/b = 1 cnvst cs, rd eoc 03057- 030 f i g u re 30. m a s t e r s e ri al d a t a tim i ng f o r r e adi n g (r ead pr ev i o us convers i on duri ng co nve r t )
ad7654 rev. a | page 21 of 28 slave serial interface extern al c l oc k the ad7654 is co nf igur ed t o accep t an ext e r n al l y s u p p lied seri al da t a c l oc k o n th e sclk p i n w h en t h e ext / int pi n i s he ld hig h . i n t h is m o de , s e v e ral m e t h o d s can be us e d t o r e ad t h e da t a . th e ext e r n al s e r i al clo c k is ga t e d b y cs . w h en bot h cs a nd rd a r e lo w , t h e da t a can b e r e ad a f t e r each con v ersio n o r d u r i n g t h e fol l o w i n g con v ersion. th e exter n al clo c k can b e e i t h e r a c o n t i n u o u s or d i s c on t i n u ou s cl o c k . a d i s c on t i n u ou s c l o c k can b e ei t h er n o r m al l y hig h o r n o r m al l y lo w w h en i n a c t i v e . fi g u r e 3 2 a n d fi g u r e 3 3 s h ow t h e d e t a i l e d t i m i n g d i ag r a ms of t h e s e me t h o d s . w h ile t h e ad7 654 is p e r f o r min g a b i t decisio n , i t is im p o r t a n t th a t v o l t a g e tra n si e n ts n o t occ u r o n d i g i tal i n p u t / o u t p u t p i n s o r deg r a d a t io n o f t h e con v ersion r e su l t co u l d o c c u r . this is p a rt i c u l a r l y i m p o rt a n t d u ri n g th e s e c o n d h a l f o f t h e c o n v e r s i o n p h as e o f eac h cha nne l bec a us e th e ad7654 p r o v ides er r o r co rr ecti o n ci r c ui tr y th a t ca n co rr ect f o r a n i m p r o p e r b i t de cisio n made d u r i n g t h e f i rs t half o f t h e con v ersio n phas e . f o r t h is r e as o n , i t is r e co mm e nde d t h a t w h e n an exter n a l clo c k is p r o v id e d , i t is a dis c o n t i n u o u s clo c k t h a t is t o g g lin g o n ly w h e n b u s y is lo w o r , m o r e im p o r t a n t l y , tha t i t do es no t tra n si tion d u r i ng t h e l a tte r h a l f of eo c hig h . extern al discontinuous clo c k data read after con v ert th oug h t h e maxim u m thr o ug h p u t ca nn on be ac hiev e d in this m o de, i t is t h e m o st r e co m m e n de d o f t h e s e r i a l sl a v e m o des. f i gur e 32 sh o w s th e d e ta iled t i m i n g di a g ra m s o f th i s m e t h od . af ter a co n v ersi o n is co m p lete, indi ca te d b y b u s y r e t u r n in g lo w , t h e co n v ersio n r e s u l t s can b e r e ad w h i l e b o t h cs and rd a r e lo w . d a t a is shif t e d o u t f r o m b o t h chan n e l s ms b f i rst, w i t h 32 clo c k p u ls es, a nd is va l i d o n b o t h r i sin g an d fa l l in g e d ges o f th e c l ock . a m o n g t h e a d va n t a g e s o f th i s m e th od i s t h e fact th a t co n v ersio n p e r f o r ma n c e is n o t deg r ade d b e c a us e t h er e a r e n o v o l t a g e t r a n sie n ts o n t h e dig i t a l in t e r f ace d u r i n g t h e con v ersion p r o c es s. an ot h e r ad va n t a g e is t h e ab i l i t y t o r e ad t h e da t a a t an y sp e e d up to 4 0 m h z , w h i c h a c c o mmo da te s b o t h sl ow d i g i t a l h o s t i n ter f ace and t h e fast es t s e r i al r e ading. f i nal l y , in this m o de o n l y , t h e ad7654 p r o v ides a da isy-c h a i n f e a t ur e usin g t h e rd c/s d in in p u t p i n f o r cas c adin g m u l t i p le co n v er t e rs t o g e t h er . this fe a t ur e is us ef u l fo r r e d u cin g c o m po nen t co un t a n d wir i n g c o nn ec t i o n s when i t is desir e d , as i t is fo r in st an ce, in i s ola t e d m u l t icon v e r t er a p plic a t io n s . an ex a m ple o f t h e conca t e n a t ion o f tw o d e vices is sho w n i n f i gur e 31. s i m u l t a n eo us s a m p lin g is p o s s ib le b y usin g a co mm on c n v s t sig n al . i t sh o u ld b e n o t e d tha t th e rd c / s d in i n put i s l a tc he d on t h e e d g e of s c l k opp o s i te t h e o n e u s e d to s h if t o u t t h e da t a o n s d o u t . th er efo r e , t h e m s b o f t h e u p s t r e a m co n v er t e r f o llo w s th e l s b o f th e d o wn s t r e a m co n v er t e r o n t h e n e xt s c lk c y cle . busy busy ad7654 #2 (upstream) ad7654 #1 (downstream) rdc/sdin sdout cnvst cs sclk rdc/sdin sdout cnvst cs sclk data out sclk in cs in cnvst in busy out 03057-033 f i g u re 31. t w o a d 7 6 5 4 s in a d a is y- ch ain conf ig ur at i o n extern al cloc k dat a r e ad ( p revio u s) d u ri ng convert f i gur e 33 sh o w s th e d e ta iled t i m i n g di a g ra m s o f th i s m e t h od . duri n g a co n v er s i o n , wh ile bo t h cs a nd rd are l o w , t h e re su lt o f t h e p r e v io us co n v ersio n ca n b e r e ad . the da t a is s h if t e d ou t, ms b f i rst, wi t h 32 clo c k p u ls es, a nd is va l i d o n b o t h r i sin g an d fal l in g e d g e s o f t h e clo c k. the 3 2 b i ts ha v e t o b e r e ad b e fo r e t h e c u r r en t co n v ersio n is co m p le t e d; o t h e r w is e , r d error is pu l s e d h i g h a n d c a n b e u s e d to i n te r r upt t h e ho st i n te r f a c e to p r e v en t i n co m p let e da t a r e ading. th er e is n o da isy-cha i n fe a t ur e i n t h is m o de, and rd c/s d in in p u t sh o u ld a l w a y s b e ti ed ei t h e r h i g h o r l o w . t o r e d u ce per f o r ma n c e degrada t io n d u e t o dig i ta l acti vi ty , a fast dis c o n t i n u ous c l o c k ( a t le ast 32 m h z in i m p u ls e mo de and 40mhz in n o r m a l mo de) is r e co m m e n de d t o en sur e tha t a l l o f th e bit s a r e r e ad d u r i n g t h e f i rs t half o f e a ch con v ersio n phas e ( eo c hig h , t 11 , t 12 ). i t is a l s o p o ssi b l e to b e g i n to r e a d da t a a f ter con v ersio n a nd co n t in ue t o r e ad t h e l a s t b i t s a f t e r a n e w co n v er s i o n h a s been ini t i a t e d . t h is a l lo ws t h e us e o f a slo w er clo c k sp e e d li ke 26 mh z in i m pu ls e m o de and d 30 mhz i n n o r m a l m o de.
ad7654 rev. a | page 22 of 28 cs sclk sdout ch a d15 busy sdin invsclk = 0 t 42 t 43 t 44 t 38 t 39 t 23 t 40 t 41 x 1 2 3 30 31 32 33 34 ext/int = 1 ch b d0 ch b d1 ch a d13 ch a d14 x ch a d14 x ch a d15 x ch a d13 x ch a d14 x ch a d15 x ch b d0 x ch b d1 y ch a d14 y ch a d15 rd = 0 a/b = 1 eoc 03057- 031 f i gure 32. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead a f te r co n v e r t) cnvst sdout sclk x ch a d15 12 3 3 1 3 2 t 3 t 42 t 43 t 44 t 38 t 39 t 23 busy invsclk = 0 cs ext/ int = 1 ch b d0 ch b d1 ch a d13 ch a d14 rd = 0 eoc t 10 t 11 t 13 t 12 a/ b = 1 03057- 032 f i gure 33. sl ave s e r i a l d a t a tim i ng f o r r e ading (r ead p r e v ious con v ers i on d u ring con v e r t)
ad7654 rev. a | page 23 of 28 microprocessor interfacing the ad7654 is ideal l y s u i t e d f o r tradi t io nal dc m e as ur em en t ap p l i c at i o n s s u p p o r t i n g a m i c r o p r o c e s s o r , a n d f o r a c s i g n a l p r oce s si n g a p p l ica t i o n s in t e rfa c in g t o a di gi tal sign al p r oce s so r . the ad7654 is desig n ed t o in ter f ace wi t h ei t h er a p a ral l e l 8-b i t o r 1 6 - b i t w i d e i n t e r f a c e , a g e n e r a l - p u rp o s e s e ri a l p o rt , o r i / o p o r t s on a m i c r o c on t r o l l e r . a v a r i e t y of e x te r n a l bu f f e r s c a n b e us ed wi t h t h e ad7654 t o p r ev en t dig i tal n o is e f r o m co u p lin g in t o t h e ad c. the fol l o w in g s e c t io n i l l u s t ra t e s t h e us e o f t h e ad7654 wi t h an s p i-e q ui p p e d ds p , t h e ads p -219x. spi interface (adsp-219x) f i gur e 34 sh o w s a n in t e r f ac e diag ra m betw e e n t h e ad7654 an d th e s p i eq u i p p e d ads p -219x. t o acco mmo da te th e s l o w er s p eed o f t h e ds p , the ad7654 ac ts as a sl a v e de vice and da ta m u s t be r e ad a f t e r co n v er si o n . th i s m o d e also al lo w s t h e d a i s y- cha i n fe a t ur e. t h e con v er t co m m a nd can b e i n i t ia te d in re sp ons e to a n i n te r n a l t i me r i n te r r upt . t h e 3 2 - b i t out p ut da t a i s r e a d w i th t w o se ri al pe ri p h e r al i n t e rf a c e ( s p i ) 1 6 - b i t wi d e acces s . the r e adin g p r o c es s ca n b e ini t i a t e d i n r e s p o n s e t o t h e end-o f -con v e rsi o n sig n a l (b us y go in g lo w) usin g a n in t e r r u p t line o f the ds p . the s e r i al in ter - face (s p i ) o n t h e ads p -219x is co nf igur e d fo r mast er m o de ( ms tr) = 1, c l o c k p o la r i ty b i t (cpol) = 0, c l o c k phas e b i t ( c ph a) = 1, and s p i i n t e r r u p t ena b le (tim od) = 00b y wr i t in g t o t h e s p i co n t r o l r e g i s t er (s p i cl tx). t o m e e t al l t i min g r e q u ir emen t s , t h e sp i clo c k s h o u l d be limi te d t o 17 mb ps, w h ic h al lo ws i t t o r e ad a n ad c r e s u l t in les s than 1 s. w h en a hig h er s a m p l i ng ra t e is desir e d , us e o f o n e o f t h e p a ral l e l i n t e r f ace m o des is r e c o mm e nde d. ad7654* adsp-219x* ser/par pfx misox sckx pfx or tfsx busy sdout sclk cnvst ext/int cs rd invsclk dvdd *additional pins omitted for clarity spixsel (pfx) 03057-034 f i gure 34. inte r f acing the ad7654 to s p i inter f ac e
ad7654 rev. a | page 24 of 28 application hints layout the ad7654 has very good immunity to noise on the power supplies. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7654 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. digital and analog ground planes should be joined in only one place, preferably underneath the ad7654, or as close as possible to the ad7654. if the ad7654 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7654. running digital lines under the device should be avoided since these couple noise onto the die. the analog ground plane should be allowed to run under the ad7654 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this reduces the effect of crosstalk through the board. the power supply lines to the ad7654 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplys impedance presented to the ad7654 and to reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supply pinavdd, dvdd, and ovddclose to, and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 f capacitors should be located near the adc to further reduce low frequency ripple. the dvdd supply of the ad7654 can be a separate supply or can come from the analog supply avdd or the digital interface supply ovdd. when the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is available, the user should connect dvdd to avdd through an rc filter (see figure 18) and the system supply to ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. the ad7654 has five different ground pins: ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. agnd is the ground to which most internal adc analog signals are referenced; it must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. evaluating the ad7654s performance a recommended layout for the ad7654 is outlined in the documentation of the evaluation board for the EVAL-AD7654CB . the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the eval-control-brd2 .
ad7654 rev. a | page 25 of 28 outline dimensions compliant to jedec standards ms-026bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 7.00 bsc sq 1.60 max 0.75 0.60 0.45 view a 9.00 bsc sq pin 1 0.20 0.09 1.45 1.40 1.35 0.08 max coplanarity view a rotated 90 ccw seating plane 7 3. 5 0 0.15 0.05 fig u re 3 5 . 48-l e ad low pr of il e qu ad f l at pa ck ag e [lqfp] (st-48) dim e nsio ns sho w n i n mi ll im e t er s compliant to jedec standards mo-220-vkkd-2 pin 1 indicator top view 6.75 bs c s q 7.00 bsc sq 1 48 12 13 37 36 24 25 5.25 5.10 sq 4.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 seating plane paddle connected to agnd. this connection is not required to meet the electrical performances 0. 2 5 m i n 0. 2 0 r e f exposed pad (bo tt om view) fig u re 3 6 . 48-l e ad lead f r a m e chip s c a l e pa ck ag e [lfcs p ] (cp-48) dim e nsio ns sho w n i n mi ll im e t er s ordering guide model temperature r a nge package descri ption package option ad7654ast C40c to +85c low profile quad flat package [lqfp] st-48 ad7654astrl C40c to +85c low profil e quad flat package [lqfp] st-48 ad7654acp C40c to +85c lead frame chip scale package [lfcsp] cp-48 ad7654acprl C40c to +85c lead frame chip scale package [lfcsp] cp-48 eval-ad7654c b 1 evaluation bo ar d eval-control brd2 2 controll er boar d 1 th i s boa r d ca n be use d a s a st a n da lon e eva l ua t i on boa r d or i n con j u n c t i on wi t h t h e eval- c on t r ol- b r d 2 for eva l u a t i on /dem on st ra t ion purpose s . 2 th i s boa r d a l low s a p c t o con t r ol a n d c o m m u n i ca t e wi t h all an a l og d e vi ce s e v a l ua t i on boa r ds e n di n g i n t h e cb de s i gn a t ors.
ad7654 rev. a | page 26 of 28 notes
ad7654 rev. a | page 27 of 28 notes
ad7654 rev. a | page 28 of 28 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c03057-0-11/04(a)

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